1. Field of the Invention
The present invention is directed to a digital filter which varies the dynamic range of coefficients used therein in order to reduce the size of hardware required to implement the filter. In particular, the invention is directed to a digital filter which adjusts coefficients thereof in accordance with a filter gain, which multiplies each adjusted coefficient by input data and adds the resulting products, and which adjusts the sum of the products in accordance with an inverse of the filter gain.
2. Description of the Related Art
Conventional digital filters, such as finite impulse response (hereinafter xe2x80x9cFIRxe2x80x9d) filters, are comprised of a plurality of filter cells, or xe2x80x9ctapxe2x80x9d cells, arranged in series. Each filter cell includes a data register for storing a sampled data value and a coefficient register which stores a coefficient for that particular cell. In operation, the same sampled data value is input sequentially to each filter cell, and is multiplied by a coefficient for that cell. The results of these multiplications are then output and combined in order to generate the filter""s output. In certain types of digital filters, known as xe2x80x9cadaptivexe2x80x9d filters, adaptation circuit is also included in each filter cell, which is used to update the cell""s coefficients based on a variety of factors, such as channel characteristics or the like, that could affect data transmission.
Problems arise in conventional digital filters due to the way in which such filters multiply the coefficients by the input data. More specifically, conventional digital filters, and in particular adaptive digital filters, often require relatively high bit precision. One way in which to obtain such precision is to use floating point arithmetic to effect the foregoing multiplication. However, floating point arithmetic can require excessive amounts of hardware to implement and can be relatively slow. As a result, floating point arithmetic has proven unsuitable for use in many digital filter applications.
Another way in which conventional digital filters obtain high bit precision is to perform the foregoing multiplication using coefficients that have a relatively large number of bits, i.e., coefficients that have a relatively large dynamic range. In order to process such large numbers of bits, however, these conventional digital filters require relatively large multiplier circuits. As a result, such digital filters also can be relatively large in size. This size constraint can be problematic, particularly in devices such as adaptive equalizers, which require tens or even hundreds of filter tap cells. Moreover, the size of the multiplier circuits used in this type of conventional digital filter also decreases the speed at which those filters operate.
Thus, there exists a need for a way to maintain high bit precision in a digital filter without significantly increasing the size and/or amount of circuitry used in the digital filter, and without significantly decreasing the speed of the digital filter.
The present invention addresses the foregoing need by providing a digital filter which adjusts coefficients in accordance with a gain prior to multiplying the coefficients by the input data. For example, in accordance with the invention, a coefficient whose magnitude has a binary representation of xe2x80x9c00000111xe2x80x9d can be adjusted to xe2x80x9c111xe2x80x9d by eliminating the first five zeros, without affecting the value of the coefficient. Using adjusted coefficients such as this, less bit precision is required during multiplication, thereby reducing the size of the multiplication circuit required to perform the multiplication, and increasing the speed at which the multiplication is performed. Moreover, in accordance with the invention, a filter output generated based on results of the multiplication is adjusted based on the inverse of the gain used to adjust the coefficients. As a result, high bit precision is maintained by the filter.
Thus, according to one aspect, the present invention is a digital filter that includes a plurality of filter cells, each of which includes circuitry to determine a coefficient for the filter cell, to adjust the coefficient in accordance with a gain that is used by each of the plurality of filter cells, and to multiply input data by the adjusted coefficient in order to generate a filter cell output. Also included in the digital filter are an adder circuit which generates a filter output by adding filter cell outputs from each of the plurality of filter cells, and an inverse gain circuit which adjusts the filter output in accordance with an inverse of the gain used to adjust the coefficients of the plurality of filter cells.
In preferred embodiments of the invention, the digital filter includes a gain control circuit to determine the gain based on a coefficient of the plurality of filter cells having a highest-order nonzero magnitude bit. In these embodiments of the invention, each of the plurality of filter cells includes a multiplier circuit to multiply the input data by the adjusted coefficient in order to generate the filter cell output, and the gain is determined so that the adjusted coefficient in each filter cell occupies an input range of the multiplier circuit for the filter cell. To this end, each of the plurality of filter cells includes a gain adjusting circuit which adjusts the coefficient for the filter cell by shifting bits comprising the coefficient such that a highest order nonzero magnitude bit of the coefficient is in a most significant bit position of an input to the multiplier circuit. By virtue of these features of the invention, it is possible to reduce the bit precision of the coefficient, e.g., by eliminating unnecessary zeros in the binary representation of the coefficient, and to thereby reduce the size of the multiplier circuit used during the multiplication described above.
In particularly preferred embodiments of the invention, the gain adjusting circuit comprises a barrel shifter which is implemented using a matrix of pass transistors. By implementing the barrel shifter using a matrix of pass transistors, the size of the barrel shifter can be reduced, thereby reducing the overall size of the digital filter even further.
According to another aspect, the present invention is a method of filtering input data using a digital filter comprised of a plurality of filter cells, where each of the plurality of filter cells generates a filter cell output based on input data and a coefficient. The method includes a coefficient determining step for determining a coefficient of each of the plurality of filter cells, a coefficient adjusting step for adjusting the coefficient of each filter cell in accordance with a gain that is used by each of the plurality of filter cells, and a multiplying step for multiplying input data in each filter cell by an adjusted coefficient so as to generate a filter cell output for each filter cell. The method also includes an adding step for adding filter cell outputs from each of the plurality of filter cells so as to generate a filter output, and an output adjusting step for adjusting the filter output in accordance with an inverse of the gain used to adjust the coefficients of the plurality of filter cells.
By adjusting the coefficient of each filter cell in accordance with a gain that is used by each of the plurality of filter cells, and then subsequently adjusting the filter output in accordance with an inverse of the gain used to adjust the coefficients, the invention is able to maintain bit precision of the filter without using excessive amounts of hardware to do so. Moreover, a digital filter which uses the method described above can be made smaller than, and can operate faster than, its conventional counterparts described above.
According to another aspect, the present invention is a digital filter which includes a first plurality of filter cells, each of which includes circuitry to determine a coefficient for the filter cell, to adjust the coefficient in accordance with a first gain that is used by each of the first plurality of filter cells, and to multiply input data by the adjusted coefficient in order to generate a first filter cell output. A first adder circuit generates a first output by adding first filter cell outputs from each of the first plurality of filter cells, and a first inverse gain circuit generates a first adjusted output by adjusting the first output in accordance with an inverse of the first gain used to adjust the coefficients of the first plurality of filter cells. Also included in the digital filter are a second plurality of filter cells, each of which includes circuitry to determine a coefficient for the filter cell, to adjust the coefficient in accordance with a second gain that is used by each of the second plurality of filter cells, and to multiply input data by the adjusted coefficient in order to generate a second filter cell output. A second adder circuit generates a second output by adding second filter cell outputs from each of the second plurality of filter cells, and a second inverse gain circuit generates a second adjusted output by adjusting the second output in accordance with an inverse of the second gain used to adjust the coefficients of the second plurality of filter cells. Finally, a third adder circuit adds the first adjusted output and the second adjusted output in order to generate a filter output for the digital filter.
By virtue of the foregoing features of the invention, it is possible to adjust different coefficients in different groups of filter cells differently, and thereby increase the overall precision of the filter.
According to still another aspect, the present invention is a digital filter which includes a plurality of filter cells, each of which includes circuitry to determine a plurality of coefficients for the filter cell, to adjust each of the plurality of coefficients in accordance with a gain that is used by each of the plurality of filter cells, and to multiply a corresponding data value input to the filter cell by a corresponding adjusted coefficient in order to generate a filter cell output. In the invention, an adder circuit generates a filter output by adding filter cell outputs from each of the plurality of filter cells, and an inverse gain circuit adjusts the filter output in accordance with an inverse of the gain used to adjust the coefficients of the plurality of filter cells.
Thus, the foregoing aspect of the invention combines resource sharing with varying coefficients"" dynamic ranges. As a result, this aspect of the invention provides even further reductions in hardware, without sacrificing speed or bit precision.
This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof in connection with the attached drawings.